Known LMS algorithms have generally been implemented in a transversal or parallel manner. An example of this standard transversal LMS implementation is shown in the five-tap transversal structure for a real LMS based equalizer in prior art FIG. 1. The standard transversal LMS adaptive equalizer structure 5 includes an actual real LMS implementation 10 included within the dashed lines and a data generating and feedback section 12. The implementation of prior art FIG. 1 is used to illustrate the required computational flow of the LMS algorithm as will be described in greater detail below.
A data source 14 in the data generating section 12 generates data as ideal binary baseband data. This ideal binary baseband data is sampled N times per symbol. Each symbol sample is represented as a voltage level as opposed to a single bit. The voltage level representation is passed to an inter-symbol interference (ISI) generator 16, for example, a fixed, 3-tap filter, to simulate inter-symbol interference. The output from the inter-symbol interference generator 16 is fed to an adder block 26 which receives as its other input a signal from an additive white gaussian noise (AWGN) generator 18. The addition of the additive white gaussian noise and ISI results in a corrupted output 43 from the adder block 26. This corrupted output 43 of the ideal binary baseband symbol data is then input to the equalizer section 10.
At the same time, an uncorrupted version of the ideal binary baseband symbol data is provided from the data source 14 to a delay block 20. The uncorrupted symbol data is delayed a predetermined number of sample times and is then fed as an output 21 to summation block 22. The delayed uncorrupted data is used as an errorless reference signal for the output 23 from the equalizer section 10. In the absence of a reference signal, a soft decision is used to generate the error signal. A soft decision is generated from the output of the equalizer and assumes that the equalizer has been trained to a reasonable channel estimate. In this case, the soft decision is used as the reference. The output of the equalizer is subtracted from the reference to form the error signal. The output of adder block 22 on line 41 is multiplied by gain factor .mu. from line 42 in multiplier 24 producing the resulting error signal e(k) which is fed back 28 to the equalizer section 10.
The predetermined amount of delay time, for example in FIG. 1 a two-sample time delay, is calculated so as to place the zero time offset of the equalizer section 10 to its center tap so that the equalizer 10 can correct for both pre- and post-symbol error sources.
The equalizer section 10 includes a delay line 25 composed of a number of delay registers 27, only one of which is designated. A first tap in the equalizer section 10 includes a coefficient update multiplier 30 which receives the corrupted output of the baseband data X(k+2) and the resulting error signal e(k) on output line 28. The coefficient update multiplier 30 provides an output signal 31 to an adder 32. The adder 32 adds its previous output 33 to the new input 31 and provides the sum to a coefficient register 34. The output of the coefficient register 34 is then provided to a coefficient multiplier 36 which further receives as its other input the data sample, x(k+2). The output 39 from the coefficient multiplier 36 is provided to a summation block 38. The summation block 38 further receives each of the outputs from the other coefficient multipliers from each tap in the equalizer section 10. The summation block 38 then provides its output signal 23 to the adder 22 as described above. While only one tap in the equalizer section 10 has been described, it is readily apparent that each of the remaining taps includes the same components but receives its data sample input after being delayed an appropriate amount via the delay line 25.
The known LMS based equalizer has the purpose of negating the effects of channel-induced inter-symbol interference. This is accomplished essentially by computing running, weighted cross-correlations between the computed error of each received symbol sample and each of the received symbol samples in the equalizer's coefficient or state registers 34. Periodically, these running cross-correlations, weighted by a feedback weighing factor .mu. (fed into multiplier 24), are loaded into the finite impulse response (FIR) filter section 40 of the equalizer 10 as the FIR's coefficients. The cross-correlation used for a given filter coefficient corresponds to the symbol data sample position in delay register 25 and the relative delay of the error corresponding to that sample. In doing this, a tap weight vector update is produced.
The above-described standard transversal LMS implementation has several disadvantages or limitations. For long filter applications, the summation tree formed with the summation block 38 presents latency problems in the filter. For example, the longer the filter, the more taps in the adaptive filter and the longer becomes the latency through the summation tree. This latency causes delays in the error calculations and eventually can lead to a situation wherein the error calculation occurs after the relevant data sample has exited the filter's state register.
For high-speed and long filter applications, the summation tree 38 further limits the cascadability of the architecture. The use of cascading requires either additional external summing hardware or an ability to cascade the output of one adaptive filter stage into the summation tree of the next cascaded block. This becomes very difficult as the word widths required are a log base two function of the number of cascaded stages.
Another known digital filter employs a systolic transposed FIR architecture to perform least means squares adaptive filtering. The adaptive filter contains dual delay lines to yield a sequence of simultaneous samples of both input and output symbol samples. This filter provides a modular implementation which can be cascaded together to form a higher order filter, however, the transposed FIR architecture requires that the FIR accumulation data be of sufficient width to allow accumulation without the introduction of error. Any rounding of the accumulated data between cascaded stages can introduce significant error.
There is therefore needed an architecture for generating a digital signal processing adaptive filter which will allow for implementation and cascading of individual chips in order to provide the desired and/or required filter length, i.e., the requisite number of filter taps. The design must allow for updating of the filter coefficients independent of the filter length and under full control of the user's command. The architecture must minimize package and pin placement requirements in order to provide a cost-effective and space-saving filter.